In the manufacture of integrated circuits, in particular, during the design of very-large-scale integrated (VLSI) circuits, the complexity of preparing and validating the effectiveness of circuit and mask layouts for many millions of devices on a single chip has resulted in simulation of those layouts as a critical component of design methodologies. However, the complexity and size of such simulations results in significant turnaround time.
For example, photolithography, or lithography, is typically used to transfer patterns relating to the layout of an integrated circuit onto a wafer substrate, including, but not limited to, materials such as silicon, silicon germainium (SiGe), silicon-on-insulator (SOI), or various combinations thereof. The drive to improve performance of VLSI circuits results in increasing requirements to decrease the size of features and increase the density of layouts. This in turn increasingly requires the use of resolution-enhancement techniques (RET) to extend the capabilities of optical lithographic processes. RET includes techniques such as the use of optical proximity correction (OPC), sub-resolution-assist-feature-enhanced lithography (SRAF) and phase-shifted-mask-enhanced lithography (PSM) or alternating phase-shift mask (altPSM) technology.
Among the several forms of Resolution Enhancement Techniques (RET), the iterative Model-Based Optical Proximity Correction (MBOPC) has established itself as a method of choice for compensation of the mask shapes for lithographic process effects. Conventional MBOPC tools work include the following steps in a manner similar to the following. An initial mask layout, typically based on the circuit design layout, is provided as input to the MBOPC tool. The shapes on the mask design (henceforth referred to as the mask) are typically defined as polygons. A pre-processing step is performed that discretizes (i.e. divides) the edges of each mask shape into smaller line segments. At the heart of the MBOPC tool is a simulator that simulates the image intensity at a particular points representing each of the line segments, which is typically at the center of each of the line segments. The OPC methodology, as embodied in an OPC tool, compares the simulated image to a desired target image to be printed on the wafer, and based on the deviation of the simulated image from the target image, the OPC tool causes the segments to be moved outward or inward from the feature interior, relative to their original position on the mask shape, to compensate for the deviation of the expected (simulated) image from the target image. This process is repeated iteratively, until, as a result of the modification of the mask shapes, the image intensity at these pre-selected points matches a threshold intensity level, within a tolerance limit.
While the quality of the OPC may improve as the number of segments increases, the efficiency of an MBOPC tool may decrease as the number of segments it simulates and iterates over in each iterative step increases. The number of segments in turn depends on the number of edges in each mask shape. In a typical mask there can be billions of shapes representing devices. Each shape can be divided into hundreds of segments. If all the segments are corrected independently, it may take some where between 150,000-250,000 CPU Hours to apply RET and OPC on a mask and use verification to detect its printability. Since both hardware and software cost depends on the total usage of CPU hours, in real dollar term this can be a significant expense.
In the current art this is made more efficient by taking advantage of the original or the designer imposed hierarchy which is also known as the native hierarchy of the design, which is a hierarchical representation of a layout based on functional reuse. In traditional representations of layouts there are a lot of circuits (such as a basic latch, de-capacitors) and combination of circuits (such as memory cells) that are used and reused again and again. This representation is known as the Hierarchic Tree in the design community, for example, circuit layout 110 in FIG. 1A. Though this is referred to as a tree, it is actually stored as Directed Acyclic Graph (DAG). Referring to FIG. 2, an example of a circuit layout 110 stored as a DAG is illustrated. C1 is a prime cell, which represents the entire layout of shapes for a given level of a circuit layout. C2 and C3 represent children of the prime cell C1. Stated another way, in this example, C1 consists of many repetitions of identical instances of two different cells C2 and C3, wherein an identical instance may include a rotation of the cell. Similarly, C2 consists of multiple repetitions or instances of child cells C4 and C5. C3 consists of multiple repetitions of children cells C6 and C7, and C4 consists of multiple instances of C8 and C9 and C5 and C6 consists of multiple instances of C10. In this example of a DAG 20, cells C7, C8, C9, and C10 are leaf nodes, which are nodes that do not have children of their own. Leaf nodes, such as cells C7, C8, C9 and C10, typically represent basic polygon shapes used as building blocks for devices, but typically do not themselves have functional significance. In typical circuit layouts, non-leaf nodes represent the combination of transistors or other devices, and combinations thereof, whose functions are repeated throughout the circuit layout. Each non-leaf node is known as a Cell. The root node C1 of the DAG is known as the Prime Cell, which represents the entire layout of a layer.
There are mainly two reasons why functional hierarchy is important for a circuit layout design. First, it helps the designers to reuse their design over and over again. Second it helps to make a design very compact. The use of a functional hierarchical design can save both memory and computation time, since computations, such as circuit or lithographic process simulations, need to be performed only once for each hierarchically stored cell and the computational results for a hierarchical cell may be applied to every instance of the cell that is repeated within the layout.
During the design process, some operations may cause the original hierarchy to be lost, which is referred to as a flattening of the hierarchy. For example, FIG. 3 illustrates a hierarchy tree 30 for a root node A (i.e. the prime cell in a DAG), including non-leaf nodes B, C, D, E, and multiple occurrences of leaf nodes “shape 1”, “shape 2”, “shape 3” and “shape 4” associated with certain non-leaf nodes A through E. Since each non-leaf cell B-E represents a repeated function within the root cell A, the characteristics of root cell A may be represented by computing the characteristics of a single occurrence of each non-leaf cell B-E, and assembling these characteristics according the hierarchy in order to obtain a representation of the root cell A.
However, an operation on the design that removes the repeated functional characteristics of the non-leaf nodes B, C, D and E within root node A, will result in a flattened hierarchy tree 31 at the root node A, such that the non-leaf nodes for the tree rooted at that node A are removed, and stores all occurrences of the leaf node shapes of the leaf nodes in the flattened root node A′. In this example, the flattened hierarchy 31 now contains N occurrences of shape1, M occurrences of shape2, L occurrences of shape3 and K occurrences of shape4, where N, M, L and K are typically in the order of millions of occurrences.
Flattening increases computational and storage requirements because simulation of the characteristics of an individual non-leaf cell B-E can no longer be applied to represent the characteristics of the flattened root cell A′. Rather, all occurrences of the leaf cells, or shapes “shape1”, “shape2”, “shape3” and “shape4” must be provided within the layout of the flattened cell A′, and computations, such as a simulation, must be performed on the entire flattened cell A′ containing all occurrences of the leaf cells.
Flattening of the original or the native hierarchy may occur in both Rule-based and Model-based lithographic computation. In case of MBOPC, shapes in the region or vicinity of optical influence around the point of interest are used for computing the image intensity at the point of interest. The effective region of optical influence (ROI) is the region enclosed by a boundary that is at a distance beyond which a feature outside of that boundary in the layout does not have a substantial effect on the optical process of imaging a particular feature at the point of interest. Stated another way, features outside of the ROI boundary will have substantially insignificant effects, for practical purposes, on the optical process of imaging the particular feature around which the ROI is formed. For example, in a lithographic process with wavelength of light of 193 nm and NA=0.85, and the optical aperture of 0.75, the ROI can be 0.8-3 microns in length. The half of the ROI dimension is often referred to as the Optical Radius. In this example the Optical Radius varies from 0.4 micron to 1.5.
Now consider a shape at the boundary of a cell in the hierarchy tree. Its vicinity region may overlap two adjacent cells within the assembled or flattened layout. After OPC, a new shape may have been created, which is unique and can not be repeated anywhere in the hierarchy tree. This would mean that any further computation done on this shape may not be re-used. This contributes to a loss of hierarchy. If this happens for a number of shapes, the hierarchy may be flattened significantly.
We can also lose hierarchy in case of rules-based computations. For example, in case of the placement of both SRAF and altPSM, one needs to consider the space between two shapes. New mask shapes such as an SRAF or the phase shapes in altPSM are placed within the space between design shapes to be printed, depending on the configurations of these shapes. If the space being considered is between two design shapes to be printed are each from two different but adjacent cells, the newly created mask shapes may be unique again and may contribute to a loss of hierarchy within the mask layout.
The effect is further exacerbated by the application of strong RET methods that may comprise several RET methods applied in tandem. For example, in altPSM masks, phase regions and SRAFs may be applied in the trim mask, and the modified trim mask containing the SRAFs and phase shapes may then be further modified by MBOPC. In each stage of the application of a separate RET, the hierarchy may flatten further and the final design may not exhibit any hierarchy at all.
The conventional method of handling hierarchy in a mask design process, comprising data preparation (data prep) which may include OPC and verification, is shown in FIG. 1A. Flattening of the hierarchy may occur as a result of many of the operations performed on the mask design during data prep.
In Block 101, the hierarchy manager 100 starts with an input layout 110 having a defined functional or native hierarchy of cells. Optionally, RET (Block 101A) may be applied prior to data prep. The hierarchy manager 100 typically deals with one cell in the functional hierarchy at a time (102).
If a cell is smaller than a pre-specified size, it is merged with a neighboring cell (103). A neighboring cell is a cell that shares a geometric boundary with another cell. For example, referring to FIG. 1B, small cell 109 that is adjacent to a small neighboring cell 111 is merged to create a single cell 112 in Block 103. Note that the neighboring cells may not be residing within the same parent in the hierarchy tree. Therefore, after merging, the merged cell 112 needs to reside in a common ancestor within the hierarchy. Therefore merging two neighboring cells would typically require exploding or flattening up to the lowest common ancestor in Block 104.
Referring to FIG. 1C, a portion of the hierarchy tree 113 is illustrated, in which child cells C14 and C15 have a common ancestor cell C12, and child cells C16 and C17 have common ancestor cell C13. Cells C12 and C13 in turn have common ancestor cell C11. Here, two small neighboring cells C15 (109) and C16 (111) are merged (Block 103 in FIG. 1A) to form merged cell C18 (112). However, the neighboring cells C15 (109) and C16 (111) do not have a common ancestor. Therefore, the hierarchy is flattened to the lowest common ancestor cell. In this case, cell C11 is the lowest common ancestor for cells C14, C17 and merged cell C18 (112). Thus the non-leaf nodes C12 and C13 are removed from the hierarchy to form a new flattened hierarchy 114 in FIG. 1C comprising the common ancestor cell C11 having child cells C14, C17 and merged cell C18 (112).
If a cell is too large, it needs to be broken into several smaller cells. For example, cell 115 is larger than a predetermined size, and is split into smaller cells 116 (Block 105). This operation may increase the number of child cells at a given level of the hierarchy, but may not significantly impact the cost of computation.
Next, each cell in the hierarchy may be a candidate for a model-based operation, such as MBOPC or manufacturability rule verification, that requires a simulation of the image. Such a cell is typically associated with a band of ROI (106) prior to performing the simulation. For example, referring to FIG. 1D, cell 117 when placed within the flattened layout, has neighboring cells 117A, 117B and 117C. To simulate the image associated with an instance of a cell 117 when placed within the layout, an ROI 217 is formed around cell 117 based on its placement within the flattened layout, in which cell 117 has neighboring cells 117A, 117B and 117C. Similarly, each of the neighboring cells 117A, 117B and 117C would have an associated ROI 217A, 217B and 217C, respectively, as illustrated in FIG. 1E.
Referring to FIG. 1F, the resulting enlarged simulation cell 118 contains the original cell 117 and the ROI 217. Although the original cell 117 may be stored hierarchically, some instances of cell 117 may have an ROI 217 that includes shapes from different neighboring cells than other instances of cell 117 within the layout. For example, the cell 117B is another identical instance of cell 117, and thus may be stored as a single instance of cell 117, the ROI 217B associated with cell 117B contains different shapes from neighboring cells when placed in the geometric context of the flattened layout. Thus some instances of cell 117 with its associated ROI 217, i.e. the enlarged simulation cell 118, would have a different optical context or region of optical influence than other instances of the enlarged simulation cell 118. Therefore, the larger simulation cells 118 and resulting images associated with cell 117 may no longer be able to be stored according to the original hierarchy for cell 117, and it may be necessary to explode or flatten the lowest common ancestor cell to accommodate the simulation cells that have different optical context regions, i.e. different ROI's.
Once the simulation cells and hierarchy are fixed in this manner, the shapes in the simulation cells are typically discretized or fragmented for simulation (Block 107). RET may be optionally be applied to the simulation cell, and RET shapes may be fragmented as necessary (Block 107). Since the application of RET may further alter the context region or ROI of each cell, further flattening of the layout may occur.
After application of OPC/RET, verification of manufacturability is performed on the OPC/RET processed cells (Block 108), which also includes simulation of the OPC/RET processed cells. Thus, any flattening of the hierarchy will result in longer turnaround times for the verification process. The results of OPC and RET is then output along with the verification results (Block 109). As discussed, current model-based design processes result in the flattening of the native or functional hierarchy several times. This flattening of the functional hierarchy decreases the efficiency of the computations and increases the memory requirements to store the data. As integrated circuits continue to evolve towards increased density and complexity, the design process will accordingly become more costly and difficult to perform efficiently.
Accordingly, it would be desirable to provide a method for improving the turnaround time for computationally intensive operations in the design process or tool for designing integrated circuits, such as lithographic mask design (e.g. MBOPC), mask manufacturability verification, or circuit design, while not reducing the quality or effectiveness of a computationally intensive design tool.